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ERET -> xRET; new memory map
[riscv-tests.git] / isa / rv64si / sbreak.S
diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index bf38434115b57ff7d0f5d1c6b5f12c3b3d0a0dce..99240be53474006d6fe8c8772ca5bc13ae9aa5eb 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
 #endif