split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64si / sbreak.S

diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index dbdf7ae22dcd68fcb9d82ad13c6fef201925f10d..bf38434115b57ff7d0f5d1c6b5f12c3b3d0a0dce 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   sbreak
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
   bne t0, t1, fail