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Remove instruction width assumptions to support RVC
[riscv-tests.git]
/
isa
/
rv64si
/
scall.S
diff --git
a/isa/rv64si/scall.S
b/isa/rv64si/scall.S
index f4752d15e9dd05027e407bd612baa3d403eed58b..82ba7c0cbc81619d46a9cf8ff4f555509047cfc4 100644
(file)
--- a/
isa/rv64si/scall.S
+++ b/
isa/rv64si/scall.S
@@
-39,6
+39,7
@@
RVTEST_CODE_BEGIN
TEST_PASSFAIL
+ .align 2
stvec_handler:
li t1, CAUSE_USER_ECALL
csrr t0, scause