Update to new privileged ISA

[riscv-tests.git] / isa / rv64sv / illegal_cfg_nxpr.S

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index c61d4d9f2c1976fdbc3274ac92a4e6796428ae79..e6190c9c99bad4160351136d3e91992dcaa3f348 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3 # set exception handler
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   li a0,33
   vsetcfg a0