split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index e2164137047d0552ea6420f1a44151dd74caa625..080cd2f6b943943e27a50ee4c4a46609f33c7117 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,7 +35,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2