add hwacha exception support

[riscv-tests.git] / isa / rv64sv / illegal_vt_regid.S

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 8baa918ab343aa325cc320cebf3bbd438489db1f..e612a8623f2886cbbf3b56c5b50c5cdfb7dbc804 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -11,11 +11,11 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  mfpcr a0,cr0
-  li a1,1
-  slli a2,a1,8
-  or a0,a0,a1 # enable traps
-  mtpcr a0,cr0
+  mfpcr a3,status
+  li a4,(1 << IRQ_COP)
+  slli a4,a4,SR_IM_SHIFT
+  or a3,a3,a4 # enable IM[COP]
+  mtpcr a3,status
 
   TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
   TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)