revamp hwacha tests

[riscv-tests.git] / isa / rv64sv / ma_utsd.S

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 6bdfcd559ab026d0d9b8072edc2487189ed10160..3b9e094a77746c88130ab6482484a57a9c610fa6 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a3, dest+1
   vsd vx1, a3
-  fence.v.l
+  fence
 
 vtcode1:
   sw x2, 0(x1)
@@ -55,8 +56,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -66,7 +68,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5