relay hwacha cause/aux to scause/sbadaddr

[riscv-tests.git] / isa / rv64sv / ma_vld.S

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index bcf4b5af75bd1513db1d95b093f3053134ea6c87..85882b8b2a34a50ec17eec9ca2a9323b93d97cff 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_vld.S
 #-----------------------------------------------------------------------------
@@ -8,17 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
-
   la a3,handler
-  mtpcr a3,cr3 # set exception handler
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
@@ -42,15 +38,15 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,28
+  csrr a3, scause
+  li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  mfpcr a3,cr2
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
@@ -71,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL