relay hwacha cause/aux to scause/sbadaddr

[riscv-tests.git] / isa / rv64sv / ma_vld.S

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index d66c42f879ac0d60b559037839a4bc23863c9e70..85882b8b2a34a50ec17eec9ca2a9323b93d97cff 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_vld.S
 #-----------------------------------------------------------------------------
@@ -8,20 +10,11 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
   la a3,handler
-  csrw evec,a3 # set exception handler
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
+  csrw stvec,a3 # set exception handler
 
   vsetcfg 32,0
   li a3,4
@@ -45,15 +38,15 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
@@ -74,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL