split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / privileged_inst.S

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 65c5288a8e7e683f08f60bdb12a1722028e0b09f..e59d361fd4562410d2288f7d05248d8a915e9984 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a3, SSTATUS_PS
   csrc sstatus, a3
   la t0, 1f
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2