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Remove cache miss test from all but one AMO test
[riscv-tests.git]
/
isa
/
rv64ua
/
amoand_d.S
diff --git
a/isa/rv64ua/amoand_d.S
b/isa/rv64ua/amoand_d.S
index 13019ae64ce9ac4481934a796e95bd96aecb5705..c1148c033ce9cdbf1c05975b88956e1a3835d35a 100644
(file)
--- a/
isa/rv64ua/amoand_d.S
+++ b/
isa/rv64ua/amoand_d.S
@@
-18,13
+18,6
@@
RVTEST_CODE_BEGIN
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sd a0, 0(a3); \
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
amoand.d a4, a1, 0(a3); \
)
amoand.d a4, a1, 0(a3); \
)
@@
-33,15
+26,6
@@
RVTEST_CODE_BEGIN
# try again after a cache miss
TEST_CASE(4, a4, 0xffffffff80000000, \
li a1, 0x0000000080000000; \
# try again after a cache miss
TEST_CASE(4, a4, 0xffffffff80000000, \
li a1, 0x0000000080000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
amoand.d a4, a1, 0(a3); \
)
amoand.d a4, a1, 0(a3); \
)
@@
-62,4
+46,3
@@
RVTEST_DATA_END
.align 3
amo_operand:
.dword 0
.align 3
amo_operand:
.dword 0
- .skip 65536