Remove cache miss test from all but one AMO test

[riscv-tests.git] / isa / rv64ua / amoswap_d.S

diff --git a/isa/rv64ua/amoswap_d.S b/isa/rv64ua/amoswap_d.S
index 628f53792d3f14214e9ea2fdfba5db97a7c32408..6b07d74409932122c66c17b076f90858932c627b 100644 (file)
--- a/isa/rv64ua/amoswap_d.S
+++ b/isa/rv64ua/amoswap_d.S
@@ -18,13 +18,6 @@ RVTEST_CODE_BEGIN
     li a1, 0xfffffffffffff800; \
     la a3, amo_operand; \
     sd a0, 0(a3); \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
-    nop; nop; nop; nop; \
     amoswap.d  a4, a1, 0(a3); \
   )
 
@@ -33,15 +26,6 @@ RVTEST_CODE_BEGIN
   # try again after a cache miss
   TEST_CASE(4, a4, 0xfffffffffffff800, \
     li  a1, 0x0000000080000000; \
-    li  a4, 16384; \
-    add a5, a3, a4; \
-    ld  x0, 0(a5); \
-    add a5, a5, a4; \
-    ld  x0, 0(a5); \
-    add a5, a5, a4; \
-    ld  x0, 0(a5); \
-    add a5, a5, a4; \
-    ld  x0, 0(a5); \
     amoswap.d a4, a1, 0(a3); \
   )
 
@@ -62,4 +46,3 @@ RVTEST_DATA_END
   .align 3
 amo_operand:
   .dword 0
-  .skip 65536