Make sure that code is 4-byte aligned before disabling rvc (#100)

[riscv-tests.git] / isa / rv64uc / rvc.S

diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S
index b0766a9671abf7add918660a976d9003d11377e3..3629d1d021f8ba95e98639ebbfa45f608388c5a4 100644 (file)
--- a/isa/rv64uc/rvc.S
+++ b/isa/rv64uc/rvc.S
@@ -13,11 +13,12 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  .align 2
   .option push
   .option norvc
 
   #define RVC_TEST_CASE(n, r, v, code...) \
-    TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop)
+    TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop)
 
   // Make sure fetching a 4-byte instruction across a page boundary works.
   li TESTNUM, 2