Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv64ui / Makefrag

diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag
index fd4ac41e1a8e872f0593a7406d54b959ee45c0d7..4af25043073c363f158e1f12fa1ad07b9a9eedc6 100644 (file)
--- a/isa/rv64ui/Makefrag
+++ b/isa/rv64ui/Makefrag
@@ -6,6 +6,7 @@ rv64ui_sc_tests = \
        add addi addiw addw \
        amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
        amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+       lrsc \
        and andi \
        auipc \
        beq bge bgeu blt bltu bne \
@@ -26,27 +27,7 @@ rv64ui_sc_tests = \
        sub subw \
        xor xori \
 
-rv64ui_mc_tests = \
-       lrsc
-
-rv64ui_sc_vec_tests = \
-       add addi addiw addw \
-       and andi \
-       lui \
-       mul mulh mulhsu mulhu mulw \
-       or ori \
-       sll slli slliw sllw \
-       slt slti sltiu sltu \
-       sra srai sraiw sraw \
-       srl srli srliw srlw \
-       sub subw \
-       xor xori \
-
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
-rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
 rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
-rv64ui_p_vec_tests = $(addprefix rv64ui-p-vec-, $(rv64ui_sc_vec_tests))
-rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
-rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
 
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)