Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv64ui / lrsc.S

diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S
index ec6748c35aa24aa809c92e23797fb4f501cccb71..9422739c6c5b6768617ad93459434916c1c22148 100644 (file)
--- a/isa/rv64ui/lrsc.S
+++ b/isa/rv64ui/lrsc.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # lrsr.S
 #-----------------------------------------------------------------------------
@@ -11,43 +13,61 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
-# wait for all cores ao boot
+# get a unique core id
 la a0, coreid
 li a1, 1
-amoadd.w a2, a1, 0(a0)
-lw a3, 4(x0)
-1: lw a1, 0(a0)
-blt a1, a3, 1b
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
 
-# have each core add its coreid ao foo 1000 aimes
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+  la a0, foo; \
+  sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
+TEST_CASE( 3, a4, 1, \
+  la a0, foo; \
+  add a1, a0, 1024; \
+  lr.w a1, (a1); \
+  sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
 la a0, foo
 li a1, 1000
-1: lr.w a4, 0(a0)
-#amoadd.w x0, a2, 0(a0)
+1: lr.w a4, (a0)
 add a4, a4, a2
-sc.w a4, a4, 0(a0)
+sc.w a4, a4, (a0)
 bnez a4, 1b
 add a1, a1, -1
 bnez a1, 1b
 
-# wait for all cores ao finish
+# wait for all cores to finish
 la a0, barrier
 li a1, 1
-amoadd.w x0, a1, 0(a0)
-1: lw a1, 0(a0)
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
 blt a1, a3, 1b
 fence
 
 # expected result is 1000*ncores*(ncores-1)/2
-la a0, foo
-li a1, 500
-mul a1, a1, a3
-add a2, a3, -1
-mul a1, a1, a2
-lw a2, 0(a0)
-bne a2, a1, 1f
-RVTEST_PASS
-1: RVTEST_FAIL
+TEST_CASE( 4, a2, 0, \
+  la a0, foo; \
+  li a1, 500; \
+  mul a1, a1, a3; \
+  add a2, a3, -1; \
+  mul a1, a1, a2; \
+  lw a2, (a0); \
+  sub a2, a2, a1; \
+)
 
 TEST_PASSFAIL