Share code between rv32ui and rv64ui tests

[riscv-tests.git] / isa / rv64ui / srli.S

diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S
index 61e5da5039241b23652006890732a42697290a7f..eae25329f590390a836d04835267070100a9fdc0 100644 (file)
--- a/isa/rv64ui/srli.S
+++ b/isa/rv64ui/srli.S
@@ -17,44 +17,47 @@ RVTEST_CODE_BEGIN
   # Arithmetic tests
   #-------------------------------------------------------------
 
-  TEST_IMM_OP( 2,  srli, 0xffffffff80000000, 0xffffffff80000000, 0  );
-  TEST_IMM_OP( 3,  srli, 0x7fffffffc0000000, 0xffffffff80000000, 1  );
-  TEST_IMM_OP( 4,  srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
-  TEST_IMM_OP( 5,  srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
-  TEST_IMM_OP( 6,  srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
-
-  TEST_IMM_OP( 7,  srli, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
-  TEST_IMM_OP( 8,  srli, 0x7fffffffffffffff, 0xffffffffffffffff, 1  );
-  TEST_IMM_OP( 9,  srli, 0x01ffffffffffffff, 0xffffffffffffffff, 7  );
-  TEST_IMM_OP( 10, srli, 0x0003ffffffffffff, 0xffffffffffffffff, 14 );
-  TEST_IMM_OP( 11, srli, 0x00000001ffffffff, 0xffffffffffffffff, 31 );
-
-  TEST_IMM_OP( 12, srli, 0x0000000021212121, 0x0000000021212121, 0  );
-  TEST_IMM_OP( 13, srli, 0x0000000010909090, 0x0000000021212121, 1  );
-  TEST_IMM_OP( 14, srli, 0x0000000000424242, 0x0000000021212121, 7  );
-  TEST_IMM_OP( 15, srli, 0x0000000000008484, 0x0000000021212121, 14 );
-  TEST_IMM_OP( 16, srli, 0x0000000000000000, 0x0000000021212121, 31 );
+#define TEST_SRL(n, v, a) \
+  TEST_IMM_OP(n, srli, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a)
+
+  TEST_SRL( 2,  0xffffffff80000000, 0  );
+  TEST_SRL( 3,  0xffffffff80000000, 1  );
+  TEST_SRL( 4,  0xffffffff80000000, 7  );
+  TEST_SRL( 5,  0xffffffff80000000, 14 );
+  TEST_SRL( 6,  0xffffffff80000001, 31 );
+
+  TEST_SRL( 7,  0xffffffffffffffff, 0  );
+  TEST_SRL( 8,  0xffffffffffffffff, 1  );
+  TEST_SRL( 9,  0xffffffffffffffff, 7  );
+  TEST_SRL( 10, 0xffffffffffffffff, 14 );
+  TEST_SRL( 11, 0xffffffffffffffff, 31 );
+
+  TEST_SRL( 12, 0x0000000021212121, 0  );
+  TEST_SRL( 13, 0x0000000021212121, 1  );
+  TEST_SRL( 14, 0x0000000021212121, 7  );
+  TEST_SRL( 15, 0x0000000021212121, 14 );
+  TEST_SRL( 16, 0x0000000021212121, 31 );
 
   #-------------------------------------------------------------
   # Source/Destination tests
   #-------------------------------------------------------------
 
-  TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 );
+  TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
 
   #-------------------------------------------------------------
   # Bypassing tests
   #-------------------------------------------------------------
 
-  TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
-  TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
-  TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+  TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
 
-  TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7  );
-  TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 );
-  TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 );
+  TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
 
-  TEST_IMM_ZEROSRC1( 24, srli, 0, 32 );
-  TEST_IMM_ZERODEST( 25, srli, 33, 50 );
+  TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
+  TEST_IMM_ZERODEST( 25, srli, 33, 10 );
 
   TEST_PASSFAIL