correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / isa / rv64uv / amomax_w.S

diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index f89bed6699bab28eaeb2d983ad0a500b0dc64d03..0308991ebfe557a63be97d082fcdbe3521b62c00 100644 (file)
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0