correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / isa / rv64uv / amominu_w.S

diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 329b3549daf7e512ae66443191bb81909dc2561e..56f3a7dc68b69e89ee87e397e98bbb0845ea512d 100644 (file)
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0