correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / isa / rv64uv / amoor_d.S

diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index 800550deea334f3460fa9d1ff5feb6c67868415d..76d553c7bbdbe8ea111e3f1c86cd764d12c06208 100644 (file)
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0