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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / bltu.S
diff --git a/isa/rv64uv/bltu.S b/isa/rv64uv/bltu.S
index 562979130040f17b551424510006e2db62f7bb58..c187efdf05208fe23fb3b83b3de23ed070efc96b 100644 (file)
--- a/isa/rv64uv/bltu.S
+++ b/isa/rv64uv/bltu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------