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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / fld.S
diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index c86fbc9ac8a7c41bfdd408601e209b5f5369cc8d..d41e76122a80d2e7c7bf09b20c33024ce9e5f367 100644 (file)
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,1