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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / lbu.S
diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 166f40e7f8b754f04c82f161c8151d3ec6710120..47c226151c0c1b5b12431c69455af1d0a6e37ee1 100644 (file)
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0