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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git]
/
isa
/
rv64uv
/
lh.S
diff --git
a/isa/rv64uv/lh.S
b/isa/rv64uv/lh.S
index 910ffd35a877c056ffec82668a48dca933958995..e4ff17663821bf7cf0ec76fe7e00f52f08e559b5 100644
(file)
--- a/
isa/rv64uv/lh.S
+++ b/
isa/rv64uv/lh.S
@@
-8,7
+8,7
@@
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64U
+RVTEST_RV64U
V
RVTEST_CODE_BEGIN
vsetcfg 16,0