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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / sd.S
diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index 67b336c0165cad62981a0294b6649d45c43314aa..053c401fe24b8b7bf96e21c7c474dbcb98acf693 100644 (file)
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0