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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / sh.S
diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index e35a77b2ea552bad4164c2ab53a0e0c9ef6a6c43..25bb258dbe4b893d104a9232b2aa8e7fcac8303e 100644 (file)
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0