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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / sw.S
diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 6f883ffe219816debbfd39347e1dd79c23e954d2..8f1599b72893f5d3662e7ba6ddf655ff54c07984 100644 (file)
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0