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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / utidx.S
diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 7de7a20c7c3a722eda106e6dbf16cbf6d876550f..04391151af7c6a356c48207b3f59fa0225aa02a0 100644 (file)
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 2,0