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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / vvadd_branch.S
diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 539ba92093c31227dc2f74bb2d0f6dcfcb973e40..5f9f3a424c1a448e5d44b25a9b605f6fb8c58ffb 100644 (file)
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0