correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / isa / rv64uv / vvadd_w.S

diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index 6e194b22fe6ebc8c3616814127e4c8661c3b462d..f81c42e07a08f895cfa73ddd56dee5b74f13f2bf 100644 (file)
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0