X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=benchmarks%2Fcommon%2Fcrt.S;h=29c1d4dd1b08f90d617eee74e517daf993fc1a8c;hp=60486be41dfafcae638f574161861bbeb8c2c487;hb=6906f6f470765b8165735ed06f864e00e8d9d5ec;hpb=9fc686ae1488a596d0bed561a750396911e71b01

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 60486be..29c1d4d 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -64,13 +64,13 @@ _start:
   li  x30,0
   li  x31,0
 
-  li t0, MSTATUS_PRV1; csrc mstatus, t0    # run tests in user mode
-  li t0, MSTATUS_IE1;  csrs mstatus, t0    # enable interrupts in user mode
+  li t0, MSTATUS_MPP;  csrc mstatus, t0    # run tests in user mode
+  li t0, MSTATUS_MPIE; csrs mstatus, t0    # enable interrupts in user mode
   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
 #ifdef __riscv64
-  csrr t0, mcpuid
+  csrr t0, misa
   # make sure processor supports RV64 if this was compiled for RV64
   bltz t0, 1f
   li a0, 1234