X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=benchmarks%2Fcommon%2Fcrt.S;h=d75e81e06548df82100a010c21a6310927cadc7c;hp=fb2cc25c692b4a8565d24dc12aa67e840dd0195e;hb=d5f7bd296f72c1a75a910aff6dd9c43f4365a188;hpb=0c98ef833db1f6eead3bd9ad083d9408d2d8decb

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index fb2cc25..d75e81e 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -1,16 +1,19 @@
+# See LICENSE for license details.
+
 #include "encoding.h"
 
-  .data
-  .globl _heapend
-  .globl environ
-_heapend:
-  .word 0
-environ:
-  .word 0
+#if __riscv_xlen == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
 
-  .text
+  .section ".text.init"
   .globl _start
-
 _start:
   li  x1, 0
   li  x2, 0
@@ -44,19 +47,28 @@ _start:
   li  x30,0
   li  x31,0
 
-#ifdef __riscv64
-  li a0, SR_U64 | SR_S64
-  csrs status, a0
+  # enable FPU and accelerator if present
+  li t0, MSTATUS_FS | MSTATUS_XS
+  csrs mstatus, t0
+
+  # make sure XLEN agrees with compilation choice
+  li t0, 1
+  slli t0, t0, 31
+#if __riscv_xlen == 64
+  bgez t0, 1f
+#else
+  bltz t0, 1f
 #endif
+2:
+  li a0, 1
+  sw a0, tohost, t0
+  j 2b
+1:
 
-  # enable fp and accelerator
-  li a0, SR_EF | SR_EA
-  csrs status, a0
-
-  ## if that didn't stick, we don't have an FPU, so don't initialize it
-  csrr t0, status
-  and t0, t0, SR_EF
-  beqz t0, 1f
+#ifdef __riscv_flen
+  # initialize FPU if we have one
+  la t0, 1f
+  csrw mtvec, t0
 
   fssr    x0
   fmv.s.x f0, x0
@@ -92,53 +104,134 @@ _start:
   fmv.s.x f30,x0
   fmv.s.x f31,x0
 1:
+#endif
 
+  # initialize trap vector
   la t0, trap_entry
-  csrw evec, t0
+  csrw mtvec, t0
+
+  # initialize global pointer
+.option push
+.option norelax
+  la gp, __global_pointer$
+.option pop
 
   la  tp, _end + 63
   and tp, tp, -64
 
-  # get core id and number of cores
-  csrr a0, hartid
-  lw a1, 4(zero)
+  # get core id
+  csrr a0, mhartid
+  # for now, assume only 1 core
+  li a1, 1
+1:bgeu a0, a1, 1b
 
-  # give each core a 1KB TLS and a 127KB stack
+  # give each core 128KB of stack + TLS
 #define STKSHIFT 17
   sll a2, a0, STKSHIFT
   add tp, tp, a2
   add sp, a0, 1
   sll sp, sp, STKSHIFT
   add sp, sp, tp
-  add tp, tp, 1024
 
-  jal _init
-  unimp
+  j _init
 
+  .align 2
 trap_entry:
-  csrw sup0, t0
-  csrw sup1, t1
-  la t0, uarch_insn
-  lw t0, (t0)
-  csrr t1, epc
-  and t1, t1, ~3
-  lw t1, (t1)
-  and t1, t1, t0
-  beq t1, t0, handle_uarch_insn
-
-  # a trap occurred that shouldn't have.
-  li t0, 1337
-  csrw tohost, t0
-1:j 1b
-
-handle_uarch_insn:
-  # we trapped on an illegal uarch-specific CSR.  just skip over it.
-  csrr t1, epc
-  add t1, t1, 4
-  csrw epc, t1
-  csrr t0, sup0
-  csrr t1, sup1
-  sret
-
-uarch_insn:
-  csrr x0, uarch0
+  addi sp, sp, -272
+
+  SREG x1, 1*REGBYTES(sp)
+  SREG x2, 2*REGBYTES(sp)
+  SREG x3, 3*REGBYTES(sp)
+  SREG x4, 4*REGBYTES(sp)
+  SREG x5, 5*REGBYTES(sp)
+  SREG x6, 6*REGBYTES(sp)
+  SREG x7, 7*REGBYTES(sp)
+  SREG x8, 8*REGBYTES(sp)
+  SREG x9, 9*REGBYTES(sp)
+  SREG x10, 10*REGBYTES(sp)
+  SREG x11, 11*REGBYTES(sp)
+  SREG x12, 12*REGBYTES(sp)
+  SREG x13, 13*REGBYTES(sp)
+  SREG x14, 14*REGBYTES(sp)
+  SREG x15, 15*REGBYTES(sp)
+  SREG x16, 16*REGBYTES(sp)
+  SREG x17, 17*REGBYTES(sp)
+  SREG x18, 18*REGBYTES(sp)
+  SREG x19, 19*REGBYTES(sp)
+  SREG x20, 20*REGBYTES(sp)
+  SREG x21, 21*REGBYTES(sp)
+  SREG x22, 22*REGBYTES(sp)
+  SREG x23, 23*REGBYTES(sp)
+  SREG x24, 24*REGBYTES(sp)
+  SREG x25, 25*REGBYTES(sp)
+  SREG x26, 26*REGBYTES(sp)
+  SREG x27, 27*REGBYTES(sp)
+  SREG x28, 28*REGBYTES(sp)
+  SREG x29, 29*REGBYTES(sp)
+  SREG x30, 30*REGBYTES(sp)
+  SREG x31, 31*REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  jal handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after eret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LREG x1, 1*REGBYTES(sp)
+  LREG x2, 2*REGBYTES(sp)
+  LREG x3, 3*REGBYTES(sp)
+  LREG x4, 4*REGBYTES(sp)
+  LREG x5, 5*REGBYTES(sp)
+  LREG x6, 6*REGBYTES(sp)
+  LREG x7, 7*REGBYTES(sp)
+  LREG x8, 8*REGBYTES(sp)
+  LREG x9, 9*REGBYTES(sp)
+  LREG x10, 10*REGBYTES(sp)
+  LREG x11, 11*REGBYTES(sp)
+  LREG x12, 12*REGBYTES(sp)
+  LREG x13, 13*REGBYTES(sp)
+  LREG x14, 14*REGBYTES(sp)
+  LREG x15, 15*REGBYTES(sp)
+  LREG x16, 16*REGBYTES(sp)
+  LREG x17, 17*REGBYTES(sp)
+  LREG x18, 18*REGBYTES(sp)
+  LREG x19, 19*REGBYTES(sp)
+  LREG x20, 20*REGBYTES(sp)
+  LREG x21, 21*REGBYTES(sp)
+  LREG x22, 22*REGBYTES(sp)
+  LREG x23, 23*REGBYTES(sp)
+  LREG x24, 24*REGBYTES(sp)
+  LREG x25, 25*REGBYTES(sp)
+  LREG x26, 26*REGBYTES(sp)
+  LREG x27, 27*REGBYTES(sp)
+  LREG x28, 28*REGBYTES(sp)
+  LREG x29, 29*REGBYTES(sp)
+  LREG x30, 30*REGBYTES(sp)
+  LREG x31, 31*REGBYTES(sp)
+
+  addi sp, sp, 272
+  mret
+
+.section ".tdata.begin"
+.globl _tdata_begin
+_tdata_begin:
+
+.section ".tdata.end"
+.globl _tdata_end
+_tdata_end:
+
+.section ".tbss.end"
+.globl _tbss_end
+_tbss_end:
+
+.section ".tohost","aw",@progbits
+.align 6
+.globl tohost
+tohost: .dword 0
+.align 6
+.globl fromhost
+fromhost: .dword 0