X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=benchmarks%2Fmm%2Fmm_main.c;h=4d08b152350e33fc2a5419375a825cacce2d8acb;hp=4fb1b1bfbcda73d1c6a9c9c8841e436f2a2f0960;hb=35c6ac438af5086510fe120b575090cf8e9b917b;hpb=160bdaa323bc8f8e651f9f546822336cf17d92f5

diff --git a/benchmarks/mm/mm_main.c b/benchmarks/mm/mm_main.c
index 4fb1b1b..4d08b15 100644
--- a/benchmarks/mm/mm_main.c
+++ b/benchmarks/mm/mm_main.c
@@ -12,15 +12,9 @@ void thread_entry(int cid, int nc)
   int m, n, p;
   uint64_t s = 0xdeadbeefU;
   
-  if (have_vec) {
-    m = HCBM;
-    n = HCBN;
-    p = HCBK;
-  } else {
-    m = CBM;
-    n = CBN;
-    p = CBK;
-  }
+  m = CBM;
+  n = CBN;
+  p = CBK;
 
   t a[m*p];
   t b[p*n];
@@ -35,26 +29,17 @@ void thread_entry(int cid, int nc)
   memset(c, 0, m*n*sizeof(c[0]));
 
   size_t instret, cycles;
-  if (have_vec) {
-    for (int i = 0; i < R; i++)
-    {
-      instret = -rdinstret();
-      cycles = -rdcycle();
-      mm_rb_hwacha(m, n, p, a, p, b, n, c, n);
-      instret += rdinstret();
-      cycles += rdcycle();
-    }
-  } else {
-    for (int i = 0; i < R; i++)
-    {
-      instret = -rdinstret();
-      cycles = -rdcycle();
-      mm(m, n, p, a, p, b, n, c, n);
-      instret += rdinstret();
-      cycles += rdcycle();
-    }
+  for (int i = 0; i < R; i++)
+  {
+    instret = -read_csr(minstret);
+    cycles = -read_csr(mcycle);
+    mm(m, n, p, a, p, b, n, c, n);
+    instret += read_csr(minstret);
+    cycles += read_csr(mcycle);
   }
 
+  asm volatile("fence");
+
   printf("C%d: reg block %dx%dx%d, cache block %dx%dx%d\n",
          cid, RBM, RBN, RBK, CBM, CBN, CBK);
   printf("C%d: %d instructions\n", cid, (int)(instret));