X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=benchmarks%2Fmm%2Fmm_main.c;h=4d08b152350e33fc2a5419375a825cacce2d8acb;hp=8b6a0933f096eb8202efe48586c077726da38fb7;hb=35c6ac438af5086510fe120b575090cf8e9b917b;hpb=35cbc0eb62e016907152cd64657a16513a7fa658

diff --git a/benchmarks/mm/mm_main.c b/benchmarks/mm/mm_main.c
index 8b6a093..4d08b15 100644
--- a/benchmarks/mm/mm_main.c
+++ b/benchmarks/mm/mm_main.c
@@ -31,11 +31,11 @@ void thread_entry(int cid, int nc)
   size_t instret, cycles;
   for (int i = 0; i < R; i++)
   {
-    instret = -rdinstret();
-    cycles = -rdcycle();
+    instret = -read_csr(minstret);
+    cycles = -read_csr(mcycle);
     mm(m, n, p, a, p, b, n, c, n);
-    instret += rdinstret();
-    cycles += rdcycle();
+    instret += read_csr(minstret);
+    cycles += read_csr(mcycle);
   }
 
   asm volatile("fence");