X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Fgdbserver.py;h=17e1734010d13047c8215eba0a32b25643937b46;hp=9dfea39fda3630004109ce484b845aa90e099087;hb=HEAD;hpb=4ec77dde62f8c14df9403abf7b10a2455ea72125 diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 9dfea39..17e1734 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -6,12 +6,14 @@ import random import sys import tempfile import time +import os import targets import testlib -from testlib import assertEqual, assertNotEqual, assertIn -from testlib import assertGreater, assertTrue, assertRegexpMatches, assertLess -from testlib import GdbTest +from testlib import assertEqual, assertNotEqual, assertIn, assertNotIn +from testlib import assertGreater, assertRegexpMatches, assertLess +from testlib import GdbTest, GdbSingleHartTest, TestFailed +from testlib import assertTrue MSTATUS_UIE = 0x00000001 MSTATUS_SIE = 0x00000002 @@ -64,68 +66,132 @@ def readable_binary_string(s): return "".join("%02x" % ord(c) for c in s) class SimpleRegisterTest(GdbTest): - def check_reg(self, name): - a = random.randrange(1< 1000 and \ + local > 1000: + return + + assertGreater(interrupt_count, 1000) + assertGreater(local, 1000) + + def postMortem(self): + GdbSingleHartTest.postMortem(self) + self.gdb.p("*((long long*) 0x200bff8)") + self.gdb.p("*((long long*) 0x2004000)") + self.gdb.p("interrupt_count") + self.gdb.p("local") + +class MulticoreRegTest(GdbTest): + compile_args = ("programs/infinite_loop.S", "-DMULTICORE") + + def early_applicable(self): + return len(self.target.harts) > 1 + + def setup(self): + self.gdb.load() + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.p("$pc=_start") + + def test(self): + # Run to main + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.b("main") + self.gdb.c() + assertIn("main", self.gdb.where()) + self.gdb.command("delete breakpoints") + + # Run through the entire loop. + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.b("main_end") + self.gdb.c() + assertIn("main_end", self.gdb.where()) + + hart_ids = [] + for hart in self.target.harts: + self.gdb.select_hart(hart) + # Check register values. + hart_id = self.gdb.p("$x1") + assertNotIn(hart_id, hart_ids) + hart_ids.append(hart_id) + for n in range(2, 32): + value = self.gdb.p("$x%d" % n) + assertEqual(value, hart_ids[-1] + n - 1) + + # Confirmed that we read different register values for different harts. + # Write a new value to x1, and run through the add sequence again. + + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.p("$x1=0x%x" % (hart.index * 0x800)) + self.gdb.p("$pc=main_post_csrr") + self.gdb.c() + for hart in self.target.harts: + self.gdb.select_hart(hart) + assertIn("main", self.gdb.where()) + # Check register values. + for n in range(1, 32): + value = self.gdb.p("$x%d" % n) + assertEqual(value, hart.index * 0x800 + n - 1) + +#class MulticoreRunHaltStepiTest(GdbTest): +# compile_args = ("programs/multicore.c", "-DMULTICORE") +# +# def early_applicable(self): +# return len(self.target.harts) > 1 +# +# def setup(self): +# self.gdb.load() +# for hart in self.target.harts: +# self.gdb.select_hart(hart) +# self.gdb.p("$mhartid") +# self.gdb.p("$pc=_start") +# +# def test(self): +# previous_hart_count = [0 for h in self.target.harts] +# previous_interrupt_count = [0 for h in self.target.harts] +# # Check 10 times +# for i in range(10): +# # 3 attempts for each time we want the check to pass +# for attempt in range(3): +# self.gdb.global_command("echo round %d attempt %d\\n" % (i, +# attempt)) +# self.gdb.c_all(wait=False) +# time.sleep(2) +# self.gdb.interrupt_all() +# hart_count = self.gdb.p("hart_count") +# interrupt_count = self.gdb.p("interrupt_count") +# ok = True +# for i, h in enumerate(self.target.harts): +# if hart_count[i] <= previous_hart_count[i]: +# ok = False +# break +# if interrupt_count[i] <= previous_interrupt_count[i]: +# ok = False +# break +# self.gdb.p("$mie") +# self.gdb.p("$mip") +# self.gdb.p("$mstatus") +# self.gdb.p("$priv") +# self.gdb.p("buf", fmt="") +# self.gdb.select_hart(h) +# pc = self.gdb.p("$pc") +# self.gdb.stepi() +# stepped_pc = self.gdb.p("$pc") +# assertNotEqual(pc, stepped_pc) +# previous_hart_count = hart_count +# previous_interrupt_count = interrupt_count +# if ok: +# break +# else: +# assert False, \ +# "hart count or interrupt didn't increment as expected" + +class MulticoreRunAllHaltOne(GdbTest): + compile_args = ("programs/multicore.c", "-DMULTICORE") + + def early_applicable(self): + return len(self.target.harts) > 1 + + def setup(self): + self.gdb.select_hart(self.target.harts[0]) + self.gdb.load() + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.p("$pc=_start") + + def test(self): + if not self.gdb.one_hart_per_gdb(): + return 'not_applicable' + + # Run harts in reverse order + for h in reversed(self.target.harts): + self.gdb.select_hart(h) + self.gdb.c(wait=False) + + self.gdb.interrupt() + # Give OpenOCD time to call poll() on both harts, which is what causes + # the bug. + time.sleep(1) + self.gdb.p("buf", fmt="") + +class MulticoreRtosSwitchActiveHartTest(GdbTest): + compile_args = ("programs/multicore.c", "-DMULTICORE") + + def early_applicable(self): + return len(self.target.harts) > 1 + + def setup(self): + self.gdb.select_hart(self.target.harts[0]) + self.gdb.load() + for hart in self.target.harts: + self.gdb.select_hart(hart) + self.gdb.p("$pc=_start") + + def test(self): + if self.gdb.one_hart_per_gdb(): + return 'not_applicable' + + # Set breakpoint near '_start' label to increase the chances of a + # situation when all harts hit breakpoint immediately and + # simultaneously. + self.gdb.b("set_trap_handler") + + # Check that all harts hit breakpoint one by one. + for _ in range(len(self.target.harts)): + output = self.gdb.c() + assertIn("hit Breakpoint", output) + assertIn("set_trap_handler", output) + assertNotIn("received signal SIGTRAP", output) + +class StepTest(GdbSingleHartTest): compile_args = ("programs/step.S", ) def setup(self): @@ -403,7 +704,7 @@ class StepTest(GdbTest): def test(self): main_address = self.gdb.p("$pc") - if self.target.extensionSupported("c"): + if self.hart.extensionSupported("c"): sequence = (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24) else: sequence = (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c) @@ -412,7 +713,30 @@ class StepTest(GdbTest): pc = self.gdb.p("$pc") assertEqual("%x" % (pc - main_address), "%x" % expected) -class TriggerTest(GdbTest): +class JumpHbreak(GdbSingleHartTest): + """'jump' resumes execution at location. Execution stops again immediately + if there is a breakpoint there. + That second line can be trouble.""" + compile_args = ("programs/trigger.S", ) + + def early_applicable(self): + return self.hart.instruction_hardware_breakpoint_count >= 1 + + def setup(self): + self.gdb.load() + self.gdb.hbreak("main") + self.gdb.c() + self.gdb.command("delete 1") + + def test(self): + self.gdb.b("read_loop") + self.gdb.command("hbreak just_before_read_loop") + output = self.gdb.command("jump just_before_read_loop") + assertRegexpMatches(output, r"Breakpoint \d, just_before_read_loop ") + output = self.gdb.c() + assertRegexpMatches(output, r"Breakpoint \d, read_loop ") + +class TriggerTest(GdbSingleHartTest): compile_args = ("programs/trigger.S", ) def setup(self): self.gdb.load() @@ -434,14 +758,15 @@ class TriggerExecuteInstant(TriggerTest): self.gdb.c() assertEqual(self.gdb.p("$pc"), main_address+4) -class TriggerLoadAddress(TriggerTest): - def test(self): - self.gdb.command("rwatch *((&data)+1)") - output = self.gdb.c() - assertIn("read_loop", output) - assertEqual(self.gdb.p("$a0"), - self.gdb.p("(&data)+1")) - self.exit() +# FIXME: Triggers aren't quite working yet +#class TriggerLoadAddress(TriggerTest): +# def test(self): +# self.gdb.command("rwatch *((&data)+1)") +# output = self.gdb.c() +# assertIn("read_loop", output) +# assertEqual(self.gdb.p("$a0"), +# self.gdb.p("(&data)+1")) +# self.exit() class TriggerLoadAddressInstant(TriggerTest): """Test a load address breakpoint on the first instruction executed out of @@ -450,20 +775,27 @@ class TriggerLoadAddressInstant(TriggerTest): self.gdb.command("b just_before_read_loop") self.gdb.c() read_loop = self.gdb.p("&read_loop") - self.gdb.command("rwatch data") + read_again = self.gdb.p("&read_again") + data = self.gdb.p("&data") + self.gdb.command("rwatch *0x%x" % data) self.gdb.c() # Accept hitting the breakpoint before or after the load instruction. assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) -class TriggerStoreAddress(TriggerTest): - def test(self): - self.gdb.command("watch *((&data)+3)") - output = self.gdb.c() - assertIn("write_loop", output) - assertEqual(self.gdb.p("$a0"), - self.gdb.p("(&data)+3")) - self.exit() + self.gdb.c() + assertIn(self.gdb.p("$pc"), [read_again, read_again + 4]) + assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) + +# FIXME: Triggers aren't quite working yet +#class TriggerStoreAddress(TriggerTest): +# def test(self): +# self.gdb.command("watch *((&data)+3)") +# output = self.gdb.c() +# assertIn("write_loop", output) +# assertEqual(self.gdb.p("$a0"), +# self.gdb.p("(&data)+3")) +# self.exit() class TriggerStoreAddressInstant(TriggerTest): def test(self): @@ -472,21 +804,37 @@ class TriggerStoreAddressInstant(TriggerTest): self.gdb.command("b just_before_write_loop") self.gdb.c() write_loop = self.gdb.p("&write_loop") - self.gdb.command("watch data") - self.gdb.c() + data = self.gdb.p("&data") + self.gdb.command("watch *0x%x" % data) + output = self.gdb.c() + if "_exit (status=0)" in output: + # We ran to _exit. It looks as if we didn't hit the trigger at all. + # However this can be "correct" behavior. gdb's definition of + # "watch" is to run until the value in memory changes. To do this + # it reads the memory value when the trigger is set, and then when + # the halt happens. Because our triggers can fire just before the + # write happens, when gdb does this check the memory hasn't + # changed. So it silently resumes running. + # https://github.com/riscv/riscv-openocd/issues/295 tracks this + # problem. Until it's fixed, we're going to allow running to _exit. + return + # Accept hitting the breakpoint before or after the store instruction. assertIn(self.gdb.p("$pc"), [write_loop, write_loop + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) class TriggerDmode(TriggerTest): + def early_applicable(self): + return self.hart.honors_tdata1_hmode + def check_triggers(self, tdata1_lsbs, tdata2): - dmode = 1 << (self.target.xlen-5) + dmode = 1 << (self.hart.xlen-5) triggers = [] - if self.target.xlen == 32: + if self.hart.xlen == 32: xlen_type = 'int' - elif self.target.xlen == 64: + elif self.hart.xlen == 64: xlen_type = 'long long' else: raise NotImplementedError @@ -521,7 +869,7 @@ class TriggerDmode(TriggerTest): assertIn("clear_triggers", output) self.check_triggers((1<<6) | (1<<0), 0xfeedac00) -class RegsTest(GdbTest): +class RegsTest(GdbSingleHartTest): compile_args = ("programs/regs.S", ) def setup(self): self.gdb.load() @@ -546,7 +894,7 @@ class WriteGprs(RegsTest): self.gdb.command("info registers") for n in range(len(regs)): assertEqual(self.gdb.x("data+%d" % (8*n), 'g'), - ((0xdeadbeef<\n") - download_c.write( + length = min(2**10, self.hart.ram_size - 2048) + self.download_c = tempfile.NamedTemporaryFile(prefix="download_", + suffix=".c", delete=False) + self.download_c.write("#include \n") + self.download_c.write( "unsigned int crc32a(uint8_t *message, unsigned int size);\n") - download_c.write("uint32_t length = %d;\n" % length) - download_c.write("uint8_t d[%d] = {\n" % length) + self.download_c.write("uint32_t length = %d;\n" % length) + self.download_c.write("uint8_t d[%d] = {\n" % length) self.crc = 0 + assert length % 16 == 0 for i in range(length / 16): - download_c.write(" /* 0x%04x */ " % (i * 16)) + self.download_c.write(" /* 0x%04x */ " % (i * 16)) for _ in range(16): value = random.randrange(1<<8) - download_c.write("%d, " % value) + self.download_c.write("0x%02x, " % value) self.crc = binascii.crc32("%c" % value, self.crc) - download_c.write("\n") - download_c.write("};\n") - download_c.write("uint8_t *data = &d[0];\n") - download_c.write("uint32_t main() { return crc32a(data, length); }\n") - download_c.flush() + self.download_c.write("\n") + self.download_c.write("};\n") + self.download_c.write("uint8_t *data = &d[0];\n") + self.download_c.write( + "uint32_t main() { return crc32a(data, length); }\n") + self.download_c.flush() if self.crc < 0: self.crc += 2**32 - self.binary = self.target.compile(download_c.name, + self.binary = self.target.compile(self.hart, self.download_c.name, "programs/checksum.c") - self.gdb.command("file %s" % self.binary) + self.gdb.global_command("file %s" % self.binary) def test(self): self.gdb.load() + self.parkOtherHarts() self.gdb.command("b _exit") self.gdb.c() assertEqual(self.gdb.p("status"), self.crc) - -class MprvTest(GdbTest): - compile_args = ("programs/mprv.S", ) - def setup(self): - self.gdb.load() - - def test(self): - """Test that the debugger can access memory when MPRV is set.""" - self.gdb.c(wait=False) - time.sleep(0.5) - self.gdb.interrupt() - output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)") - assertIn("0xbead", output) - -class PrivTest(GdbTest): + os.unlink(self.download_c.name) + +#class MprvTest(GdbSingleHartTest): +# compile_args = ("programs/mprv.S", ) +# def setup(self): +# self.gdb.load() +# +# def test(self): +# """Test that the debugger can access memory when MPRV is set.""" +# self.gdb.c(wait=False) +# time.sleep(0.5) +# self.gdb.interrupt() +# output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)") +# assertIn("0xbead", output) + +class PrivTest(GdbSingleHartTest): compile_args = ("programs/priv.S", ) def setup(self): # pylint: disable=attribute-defined-outside-init self.gdb.load() - misa = self.target.misa + misa = self.hart.misa self.supported = set() if misa & (1<<20): self.supported.add(0) @@ -633,9 +985,29 @@ class PrivTest(GdbTest): self.supported.add(2) self.supported.add(3) + # Disable physical memory protection by allowing U mode access to all + # memory. + try: + self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X + self.gdb.p("$pmpaddr0=0x%x" % + ((self.hart.ram + self.hart.ram_size) >> 2)) + except testlib.CouldNotFetch: + # PMP registers are optional + pass + + # Ensure Virtual Memory is disabled if applicable (SATP register is not + # reset) + try: + self.gdb.p("$satp=0") + except testlib.CouldNotFetch: + # SATP only exists if you have S mode. + pass + class PrivRw(PrivTest): def test(self): """Test reading/writing priv.""" + # Leave the PC at _start, where the first 4 instructions should be + # legal in any mode. for privilege in range(4): self.gdb.p("$priv=%d" % privilege) self.gdb.stepi() @@ -674,7 +1046,7 @@ def main(): epilog=""" Example command line from the real world: Run all RegsTest cases against a physical FPGA, with custom openocd command: - ./gdbserver.py --freedom-e300 --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple + ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple """) targets.add_target_options(parser) @@ -683,10 +1055,8 @@ def main(): # TODO: remove global global parsed # pylint: disable=global-statement parsed = parser.parse_args() - - target = parsed.target(parsed.cmd, parsed.run, parsed.isolate) - if parsed.xlen: - target.xlen = parsed.xlen + target = targets.target(parsed) + testlib.print_log_names = parsed.print_log_names module = sys.modules[__name__]