X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Ftargets.py;h=c431a671697a4560e0bf469535b89b1ee5ccb1c7;hp=8c725c4ebdec6bbb749e23b924d32fedde7b5a11;hb=6855cddc0ff7bcc06e71aa24a0417fc0656e75fb;hpb=f8910f9e782dbc1752a7d1b94c7b18bbc04178d3

diff --git a/debug/targets.py b/debug/targets.py
index 8c725c4..c431a67 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -39,9 +39,9 @@ class Target(object):
                     prefix=binary_name + "_")
             binary_name = self.temporary_binary.name
             Target.temporary_files.append(self.temporary_binary)
-        march = "RV%dIMA" % self.xlen
+        march = "rv%dima" % self.xlen
         if self.use_fpu:
-            march += "FD"
+            march += "fd"
         testlib.compile(sources +
                 ("programs/entry.S", "programs/init.c",
                     "-I", "../env",