X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Ftargets%2Ffreedom-e300-sim%2Fopenocd.cfg;h=e8edda4e6c660392c0deb3913c5fdb30d12b0f5c;hp=767d22963de48571f4efe9bfa35bce9350897f94;hb=71c5774174e72602f0501eaf1a09b3eba162a7c1;hpb=b00a402f5d921fda37a7e5e59b8d4c566467f0a4

diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
index 767d229..e8edda4 100644
--- a/debug/targets/freedom-e300-sim/openocd.cfg
+++ b/debug/targets/freedom-e300-sim/openocd.cfg
@@ -8,12 +8,6 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
-#reset_config trst_and_srst separate
-# Stupid long so I can see the LEDs
-#adapter_nsrst_delay 2000
-#jtag_ntrst_delay 1000
-#
 init
-#reset
 
 halt