X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Ftestlib.py;h=82a731a73b7662f0765855dcb257b9ec96599416;hp=b2bfa8ed4c2bbb1acd8fb4e0e1d273415e119d6c;hb=08a051d3037c1b3232b74f8b105151f7f908fd8f;hpb=55d31b6f933bda107a399fdd169bd01a7ea5da6c;ds=sidebyside

diff --git a/debug/testlib.py b/debug/testlib.py
index b2bfa8e..82a731a 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -58,6 +58,7 @@ class Spike(object):
         if with_gdb:
             self.port = unused_port()
             cmd += ['--gdb-port', str(self.port)]
+        cmd.append("-m32")
         cmd.append('pk')
         if binary:
             cmd.append(binary)