X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv32si%2Fillegal.S;h=ad5c3b1d9c6b19865c6f112d73ce82dda4de2c44;hp=3bec030566f050367d6e704a02b65c9b1ac988ce;hb=c3378e8d37d38432947451ab26a93bb5ae7eb3a1;hpb=74bc584aa5be5d52ded54e44dbf465f63b03a629

diff --git a/isa/rv32si/illegal.S b/isa/rv32si/illegal.S
index 3bec030..ad5c3b1 100644
--- a/isa/rv32si/illegal.S
+++ b/isa/rv32si/illegal.S
@@ -1,43 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# illegal.S
-#-----------------------------------------------------------------------------
-#
-# Test illegal instruction trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  .word 0
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t1, CAUSE_ILLEGAL_INSTRUCTION
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/illegal.S"