X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv32si%2Fma_fetch.S;h=2e5254fa570fd24a69c1a89869d8325d6a9e92c9;hp=4aa7973fd805fc3852a0792ee6267155780315d2;hb=c3378e8d37d38432947451ab26a93bb5ae7eb3a1;hpb=74bc584aa5be5d52ded54e44dbf465f63b03a629

diff --git a/isa/rv32si/ma_fetch.S b/isa/rv32si/ma_fetch.S
index 4aa7973..2e5254f 100644
--- a/isa/rv32si/ma_fetch.S
+++ b/isa/rv32si/ma_fetch.S
@@ -1,61 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# ma_fetch.S
-#-----------------------------------------------------------------------------
-#
-# Test misaligned fetch trap.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
-  la t0, stvec
-  csrw stvec, t0
-
-  li TESTNUM, 2
-  la t0, 1f
-  jr t0, 2
-1:
-  j fail
-
-  li TESTNUM, 3
-  la t0, 2f
-  jr t0, 1
-2:
-  // this test should pass, since the low bit should be masked off
-
-  li TESTNUM, 4
-  la t0, 3f
-  jr t0, 3
-3:
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec:
-  li t0, 3
-  beq TESTNUM, t0, fail
-
-  li t1, CAUSE_MISALIGNED_FETCH
-  csrr t0, scause
-  bne t0, t1, fail
-  li t1, 0
-  csrr t0, sepc
-  addi t0, t0, 2 // skip over instruction after jalr
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
 
-RVTEST_DATA_END
+#include "../rv64si/ma_fetch.S"