X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv32si%2Fscall.S;h=a036aaf648e62c0a5dadd96d87438b8944649b77;hp=c5cc3ac98ce7b68d3865b53db928c1f8ac796b3b;hb=211d78276b07b17f831cefaf79961d3e6dad3c90;hpb=dd0d4036430dc812c9168fad8870d58ce151f498

diff --git a/isa/rv32si/scall.S b/isa/rv32si/scall.S
index c5cc3ac..a036aaf 100644
--- a/isa/rv32si/scall.S
+++ b/isa/rv32si/scall.S
@@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
 stvec:
-  li t1, CAUSE_SCALL
+  li t1, CAUSE_ECALL
   csrr t0, scause
   bne t0, t1, fail
   csrr t0, sepc