X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv64mi%2Fillegal.S;h=30c22b264fcadf55d66d5673e7d283fae18d9bda;hp=c5ccffde2b392885062d339a0835b7baf8f8baa4;hb=ad4010d4b7147a6607c2fd30c7885ca6b464abbc;hpb=9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index c5ccffd..30c22b2 100644
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -1,8 +1,40 @@
 # See LICENSE for license details.
 
+#*****************************************************************************
+# illegal.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal instruction trap.
+#
+
 #include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV64M
-#define __MACHINE_MODE
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  li TESTNUM, 2
+  .word 0
+  j fail
+
+  j pass
+
+  TEST_PASSFAIL
+
+mtvec_handler:
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  csrr t0, mcause
+  bne t0, t1, fail
+  csrr t0, mepc
+  addi t0, t0, 8
+  csrw mepc, t0
+  mret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
 
-#include "../rv64si/illegal.S"
+RVTEST_DATA_END