X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv64mi%2Fma_addr.S;h=ba96606335e9acd6322cbaf2eb8502d508489d09;hp=be3572fec37de1ca9be65f917c71a26f560b60e0;hb=7f5d59f657b25bdd5bebdc6c8875c8cd629dd330;hpb=7dfc16ad687186faa57368a251489e56b72b6f91

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index be3572f..ba96606 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -22,6 +22,7 @@ RVTEST_CODE_BEGIN
 
 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
   li TESTNUM, testnum; \
+  addi t1, base, offset; \
   insn x0, offset(base); \
   j fail \
 
@@ -70,6 +71,9 @@ mtvec_handler:
   csrr t0, mcause
   bne t0, s1, fail
 
+  csrr t0, mbadaddr
+  bne t0, t1, fail
+
   csrr t0, mepc
   addi t0, t0, 8
   csrw mepc, t0