X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv64ui%2Fslliw.S;h=0ed888b449892ca072d6a5e520ba85871343f931;hp=7822f0988328c8c64fca799be65f5b7154dc030e;hb=ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc;hpb=9d3bc86d85d935f498065d54ead7e568f03b2824;ds=sidebyside

diff --git a/isa/rv64ui/slliw.S b/isa/rv64ui/slliw.S
index 7822f09..0ed888b 100644
--- a/isa/rv64ui/slliw.S
+++ b/isa/rv64ui/slliw.S
@@ -35,6 +35,13 @@ RVTEST_CODE_BEGIN
   TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
   TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
 
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 );
+  TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 );
+
   #-------------------------------------------------------------
   # Source/Destination tests
   #-------------------------------------------------------------