X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv64ui%2Fsrl.S;h=c1e936a8b7eb48ec8a0fd4b6fccb9a74937d912b;hp=ad5c2e5e5b28d3aac23c92d9b1836f31e9f96e01;hb=56f46aa0f9688c87ce9ebd7658e19b884b018b6b;hpb=b68b39031a730ecc155ed87fba2ed5f111d0ab07

diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S
index ad5c2e5..c1e936a 100644
--- a/isa/rv64ui/srl.S
+++ b/isa/rv64ui/srl.S
@@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 #define TEST_SRL(n, v, a) \
-  TEST_RR_OP(n, srl, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a)
+  TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
 
   TEST_SRL( 2,  0xffffffff80000000, 0  );
   TEST_SRL( 3,  0xffffffff80000000, 1  );