X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=isa%2Frv64ui%2Fsrlw.S;fp=isa%2Frv64ui%2Fsrlw.S;h=f0d1daefe422fcc6138a1b128d9293a8b5443309;hp=24a492a144d30f74f034088883aeb9634388ab43;hb=0c0d77c594305417cd8305e17950f86da14e71c4;hpb=9d3bc86d85d935f498065d54ead7e568f03b2824

diff --git a/isa/rv64ui/srlw.S b/isa/rv64ui/srlw.S
index 24a492a..f0d1dae 100644
--- a/isa/rv64ui/srlw.S
+++ b/isa/rv64ui/srlw.S
@@ -43,6 +43,13 @@ RVTEST_CODE_BEGIN
   TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
   TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
 
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 );
+  TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 );
+
   #-------------------------------------------------------------
   # Source/Destination tests
   #-------------------------------------------------------------