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(parent: ab6c2cc) | patch
Make the debug tests aware of multicore.
authorTim Newsome <tim@sifive.com>
Mon, 7 Aug 2017 19:51:42 +0000 (12:51 -0700)
committerTim Newsome <tim@sifive.com>
Mon, 28 Aug 2017 19:16:39 +0000 (12:16 -0700)
commit3a44725d27f6b2c77f0ca912d792b6856fde6a17
treee89d52105aa01d59e7d4588ef157d477f0a4335dtree
parentab6c2ccaec192684cf4649d5d69bd105d738d1c7commit | diff
Make the debug tests aware of multicore.

Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.

There's currently only one test that tests multicore behavior, but there
could be more.

The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
18 files changed:
debug/Makefile diff | blob | history
debug/gdbserver.py diff | blob | history
debug/programs/entry.S diff | blob | history
debug/programs/start.S [deleted file] blob | history
debug/targets.py diff | blob | history
debug/targets/RISC-V/spike.cfg [new file with mode: 0644] blob
debug/targets/RISC-V/spike32-2.py [new file with mode: 0644] blob
debug/targets/RISC-V/spike32.cfg [deleted file] blob | history
debug/targets/RISC-V/spike32.py diff | blob | history
debug/targets/RISC-V/spike64-2.py [new file with mode: 0644] blob
debug/targets/RISC-V/spike64.cfg [deleted file] blob | history
debug/targets/RISC-V/spike64.py diff | blob | history
debug/targets/SiFive/Freedom/E300.py diff | blob | history
debug/targets/SiFive/Freedom/E300Sim.py diff | blob | history
debug/targets/SiFive/Freedom/U500.py diff | blob | history
debug/targets/SiFive/Freedom/U500Sim.py diff | blob | history
debug/targets/SiFive/HiFive1.py diff | blob | history
debug/testlib.py diff | blob | history