modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Oct 2018 22:41:20 +0000 (23:41 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Oct 2018 22:41:20 +0000 (23:41 +0100)
commite2e75e127edd203d4c31b0ff5d9dc6170e42d71b
tree94617e78fdf80a01ffaac93ce1d4c87f6ef5198e
parentcda71959b26639a7398b600cbb45b91c55e0f38d
modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
15 files changed:
isa/macros/simplev/sv_test_macros.h
isa/rv64uc/Makefrag.sv
isa/rv64uc/sv_c_beqz.S [new file with mode: 0644]
isa/rv64uc/sv_c_lwsp.S
isa/rv64uc/sv_c_lwsp_predication.S
isa/rv64uc/sv_c_mv.S
isa/rv64uc/sv_c_mv_predication.S
isa/rv64uc/sv_c_swsp.S
isa/rv64ud/sv_fadd.S
isa/rv64ui/sv_addi.S
isa/rv64ui/sv_addi_predicated.S
isa/rv64ui/sv_addi_redirect.S
isa/rv64ui/sv_addi_scalar_src.S
isa/rv64ui/sv_addi_vector_vector.S
isa/rv64ui/sv_beq.S