use RVTEST_RV64UF macro for FPU tests

diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h
index 8ce8490d8c24ec229dfb6e5895334292e036b03a..a537fb2494add1af1c8503476805c81c995d910d 100644 (file)
--- a/env/p/riscv_test.h
+++ b/env/p/riscv_test.h
@@ -7,6 +7,10 @@
 
 #define RVTEST_RV64U                                                    \
 
+#define RVTEST_RV64UF                                                   \
+  RVTEST_RV64U;                                                         \
+  RVTEST_FP_ENABLE
+
 #define RVTEST_RV32U                                                    \
   clearpcr cr0, 0x80
 

diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h
index fd07ead1d4fe3308a44bac639038d96365aff58b..98d058044ff25384fc62f51b303838ffd657a5ef 100644 (file)
--- a/env/pm/riscv_test.h
+++ b/env/pm/riscv_test.h
@@ -7,6 +7,10 @@
 
 #define RVTEST_RV64U                                                    \
 
+#define RVTEST_RV64UF                                                   \
+  RVTEST_RV64U;                                                         \
+  RVTEST_FP_ENABLE
+
 #define RVTEST_RV64S                                                    \
 
 #define RVTEST_FP_ENABLE                                                \

diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h
index 363e6e15ad567c7c9580e91b982c6beea7b3d701..748fe973b2dfbb062d2323f40bd5ea59781cc59b 100644 (file)
--- a/env/pt/riscv_test.h
+++ b/env/pt/riscv_test.h
@@ -9,6 +9,10 @@
 
 #define RVTEST_RV64U                                                    \
 
+#define RVTEST_RV64UF                                                   \
+  RVTEST_RV64U;                                                         \
+  RVTEST_FP_ENABLE
+
 #define RVTEST_FP_ENABLE                                                \
   setpcr cr0, 2;                                                        \
   mfpcr a0, cr0;                                                        \

diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h
index 2a1710d51ad8e341dc809147678047fa50b69b48..6aa232ede68bd04f93398ce203f4c08bf5cdfb83 100644 (file)
--- a/env/v/riscv_test.h
+++ b/env/v/riscv_test.h
@@ -6,11 +6,17 @@
 //-----------------------------------------------------------------------
 
 #define RVTEST_RV64U                                                    \
+  .text;                                                                \
+init:                                                                   \
+  ret
 
-#define RVTEST_RV64S                                                    \
-
-#define RVTEST_FP_ENABLE                                                \
+#define RVTEST_RV64UF                                                   \
+  .text;                                                                \
+init:                                                                   \
   mtfsr x0;                                                             \
+  ret
+
+#define RVTEST_RV64S                                                    \
 
 #define RVTEST_VEC_ENABLE                                               \
   mfpcr t0, cr0;                                                        \
@@ -24,7 +30,7 @@
         .align  13;                                                     \
         .global userstart;                                              \
 userstart:                                                              \
-        RVTEST_FP_ENABLE;                                               \
+        jal init
 
 //-----------------------------------------------------------------------
 // End Macro

diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S
index 58f44bee4d7f5cf242d766af292b898331326144..cced11b397cd0a36e306936efc327d5e7157f100 100644 (file)
--- a/isa/rv64uf/fadd.S
+++ b/isa/rv64uf/fadd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S
index 845db3c92537eebfdb25a67b75f8ed1cdd271819..21cbf9d3f6c7da02cb22a9a7f45e3117d62a8cbb 100644 (file)
--- a/isa/rv64uf/fcmp.S
+++ b/isa/rv64uf/fcmp.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S
index bb9a9c4794c01d59f8448a914ca64be792b747b3..0e834160f279765a4ff205192572d46c311812ae 100644 (file)
--- a/isa/rv64uf/fcvt.S
+++ b/isa/rv64uf/fcvt.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S
index e2e168656c77aae93bbc8b78b43f29137db66bd6..5492a09f4558181f2232ef09c7f3976170f9e681 100644 (file)
--- a/isa/rv64uf/fcvt_w.S
+++ b/isa/rv64uf/fcvt_w.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S
index 76e5e9f542ce8343d59d177af5491ae23400374f..dc16ecb9b0b40bc3144c9fa323c1f3f9196a0763 100644 (file)
--- a/isa/rv64uf/fmadd.S
+++ b/isa/rv64uf/fmadd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S
index 0041ea5fcb3d5feb6c78a5936b0ac801f36046e1..f9e8dda1bbe93d637794211529f56cd9044ef812 100644 (file)
--- a/isa/rv64uf/fmin.S
+++ b/isa/rv64uf/fmin.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S
index 0d2124b157cf21f19adc25039fe8fba4ae45b1d3..d4055649c908b3c76b055aee520014310684d7bc 100644 (file)
--- a/isa/rv64uf/fsgnj.S
+++ b/isa/rv64uf/fsgnj.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------

diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S
index f37a4787157458670abf77ff9a439418fa701371..653344bafbcb3534283d508ed95e8d1b1b79bb60 100644 (file)
--- a/isa/rv64uf/ldst.S
+++ b/isa/rv64uf/ldst.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
   TEST_CASE(2, a0, 0x4000000040400000, la a1, tdat; flw f1, 4(a1); fsw f1, 12(a1); ld a0, 8(a1))

diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S
index f06e324810d56d52598da2735758936e4c9df70a..d8ad24cad5a66a28e9bbc0db2b3ef59676af2e6c 100644 (file)
--- a/isa/rv64uf/move.S
+++ b/isa/rv64uf/move.S
@@ -9,7 +9,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
 li a0, 1

diff --git a/isa/rv64uf/structural.S b/isa/rv64uf/structural.S
index 0c74ab554be04bc26fb8dda1af8c86d6923ce66c..24a5687f4525833aa9880180f14be314310757ca 100644 (file)
--- a/isa/rv64uf/structural.S
+++ b/isa/rv64uf/structural.S
@@ -9,7 +9,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UF
 RVTEST_CODE_BEGIN
 
 li x25, 1