Reference TESTNUM instead of x28 directly

diff --git a/env b/env
index 746361936518f56549726c3e661606e5f28a1b96..217bb5eef46deb0eeac7b8f11c9d36d9310feabb 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 746361936518f56549726c3e661606e5f28a1b96
+Subproject commit 217bb5eef46deb0eeac7b8f11c9d36d9310feabb

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index 10680d47b9fd64be17a7b358e4b0216af4fc8551..dca9a92cc0e3923defd9599ce95140489ebeb650 100644 (file)
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -10,14 +10,14 @@
 test_ ## testnum: \
     code; \
     li  x29, correctval; \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     bne testreg, x29, fail;
 
 #define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
 test_ ## testnum: \
     code; \
     li  x29, correctval; \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     beq testreg, x29, pass_ ## testnum; \
     j fail; \
 pass_ ## testnum: \
@@ -264,7 +264,7 @@ pass_ ## testnum: \
 
 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, base; \
     inst x3, offset(x1); \
@@ -278,7 +278,7 @@ test_ ## testnum: \
 
 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, base; \
     TEST_INSERT_NOPS_ ## nop_cycles \
@@ -291,7 +291,7 @@ test_ ## testnum: \
 
 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x1, result; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -307,7 +307,7 @@ test_ ## testnum: \
 
 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x2, base; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -327,28 +327,28 @@ test_ ## testnum: \
 
 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     inst x1, 2f; \
-    bne x0, x28, fail; \
-1:  bne x0, x28, 3f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
 2:  inst x1, 1b; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 3:
 
 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     inst x1, 1f; \
-    bne x0, x28, 2f; \
-1:  bne x0, x28, fail; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
 2:  inst x1, 1b; \
 3:
 
 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x1, val1; \
     TEST_INSERT_NOPS_ ## nop_cycles \
@@ -359,30 +359,30 @@ test_ ## testnum: \
 
 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     li  x2, val2; \
     inst x1, x2, 2f; \
-    bne x0, x28, fail; \
-1:  bne x0, x28, 3f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
 2:  inst x1, x2, 1b; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 3:
 
 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x1, val1; \
     li  x2, val2; \
     inst x1, x2, 1f; \
-    bne x0, x28, 2f; \
-1:  bne x0, x28, fail; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
 2:  inst x1, x2, 1b; \
 3:
 
 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x1, val1; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -395,7 +395,7 @@ test_ ## testnum: \
 
 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  li  x2, val2; \
     TEST_INSERT_NOPS_ ## src1_nops \
@@ -412,24 +412,24 @@ test_ ## testnum: \
 
 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x6, 2f; \
     TEST_INSERT_NOPS_ ## nop_cycles \
     inst x6; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 2:  addi  x4, x4, 1; \
     li  x5, 2; \
     bne x4, x5, 1b \
 
 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 test_ ## testnum: \
-    li  x28, testnum; \
+    li  TESTNUM, testnum; \
     li  x4, 0; \
 1:  la  x6, 2f; \
     TEST_INSERT_NOPS_ ## nop_cycles \
     inst x19, x6, 0; \
-    bne x0, x28, fail; \
+    bne x0, TESTNUM, fail; \
 2:  addi  x4, x4, 1; \
     li  x5, 2; \
     bne x4, x5, 1b \
@@ -445,7 +445,7 @@ test_ ## testnum: \
 
 #define TEST_FP_OP_S_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   flw f0, 0(a0); \
   flw f1, 4(a0); \
@@ -464,7 +464,7 @@ test_ ## testnum: \
 
 #define TEST_FP_OP_D_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   fld f0, 0(a0); \
   fld f1, 8(a0); \
@@ -531,7 +531,7 @@ test_ ## testnum: \
 
 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   lw  a3, 0(a0); \
   li  a0, val1; \
@@ -546,7 +546,7 @@ test_ ## testnum: \
 
 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 test_ ## testnum: \
-  li  x28, testnum; \
+  li  TESTNUM, testnum; \
   la  a0, test_ ## testnum ## _data ;\
   ld  a3, 0(a0); \
   li  a0, val1; \
@@ -591,7 +591,7 @@ vtcode2 ## testnum: \
   stop; \
 handler ## testnum: \
   vxcptkill; \
-  li x28,2; \
+  li TESTNUM,2; \
   vxcptcause a0; \
   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
   bne a0,a1,fail; \
@@ -613,16 +613,16 @@ handler ## testnum: \
   fence; \
   ld a1,0(a3); \
   li a2,5; \
-  li x28,2; \
+  li TESTNUM,2; \
   bne a1,a2,fail; \
   ld a1,8(a3); \
-  li x28,3; \
+  li TESTNUM,3; \
   bne a1,a2,fail; \
   ld a1,16(a3); \
-  li x28,4; \
+  li TESTNUM,4; \
   bne a1,a2,fail; \
   ld a1,24(a3); \
-  li x28,5; \
+  li TESTNUM,5; \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
@@ -651,7 +651,7 @@ vtcode2 ## testnum: \
   stop; \
 handler ## testnum: \
   vxcptkill; \
-  li x28,2; \
+  li TESTNUM,2; \
   vxcptcause a0; \
   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
   bne a0,a1,fail; \
@@ -672,24 +672,24 @@ handler ## testnum: \
   fence; \
   ld a1,0(a3); \
   li a2,5; \
-  li x28,2; \
+  li TESTNUM,2; \
   bne a1,a2,fail; \
   ld a1,8(a3); \
-  li x28,3; \
+  li TESTNUM,3; \
   bne a1,a2,fail; \
   ld a1,16(a3); \
-  li x28,4; \
+  li TESTNUM,4; \
   bne a1,a2,fail; \
   ld a1,24(a3); \
-  li x28,5; \
+  li TESTNUM,5; \
   bne a1,a2,fail; \
 
 #-----------------------------------------------------------------------
-# Pass and fail code (assumes test num is in x28)
+# Pass and fail code (assumes test num is in TESTNUM)
 #-----------------------------------------------------------------------
 
 #define TEST_PASSFAIL \
-        bne x0, x28, pass; \
+        bne x0, TESTNUM, pass; \
 fail: \
         RVTEST_FAIL \
 pass: \

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 932aba3c4affeeaa95eb8c6dc1aac44148906b18..5a8f0a157bf5225d4cc542ed05362453ccee8d41 100644 (file)
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -25,7 +25,7 @@ test_ ## testnum: \
   fence; \
   li a1,correctval; \
   li a2,0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -238,7 +238,7 @@ test_ ## testnum: \
   fence; \
   lw  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   lw a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -278,7 +278,7 @@ test_ ## testnum: \
   fence; \
   ld  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -352,7 +352,7 @@ test_ ## testnum: \
   la  a5, test_ ## testnum ## _data ;\
   lw  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   lw a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -385,7 +385,7 @@ test_ ## testnum: \
   la  a5, test_ ## testnum ## _data ;\
   ld  a1, 0(a5); \
   li a2, 0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -533,7 +533,7 @@ test_ ## testnum: \
   fence; \
   li a1,correctval; \
   li a2,0; \
-  li x28, testnum; \
+  li TESTNUM, testnum; \
 test_loop ## testnum: \
   ld a0,0(a4); \
   beq a0,a1,skip ## testnum; \
@@ -591,11 +591,11 @@ next ## testnum :
                  )
 
 #-----------------------------------------------------------------------
-# Pass and fail code (assumes test num is in x28)
+# Pass and fail code (assumes test num is in TESTNUM)
 #-----------------------------------------------------------------------
 
 #define TEST_PASSFAIL \
-        bne x0, x28, pass; \
+        bne x0, TESTNUM, pass; \
 fail: \
         RVTEST_FAIL \
 pass: \

diff --git a/isa/rv32ui/j.S b/isa/rv32ui/j.S
index 0a4ca320744c4c66263ae40ecc515874b28e3dde..ff1de6555cddeb45e75a3287b2035b7018f1e50e 100644 (file)
--- a/isa/rv32ui/j.S
+++ b/isa/rv32ui/j.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
   # Test basic
   #-------------------------------------------------------------
 
-  li  x28, 2;
+  li  TESTNUM, 2;
   j test_2;
   j fail;
 test_2:

diff --git a/isa/rv32ui/jal.S b/isa/rv32ui/jal.S
index c4c0af977d7755f1d377dfc21e538e72eb8ed953..6055000adeea0384986c17a706d1ab90a4e9380b 100644 (file)
--- a/isa/rv32ui/jal.S
+++ b/isa/rv32ui/jal.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  ra, 0
 
 linkaddr_2:

diff --git a/isa/rv32ui/jalr.S b/isa/rv32ui/jalr.S
index 2d6d3a7de18b54c9c0c4dae00b67318934c092ba..e65fd7945b0bf068ffe548b185fbc627b5bb41ba 100644 (file)
--- a/isa/rv32ui/jalr.S
+++ b/isa/rv32ui/jalr.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  x31, 0
   la  x2, target_2
 
@@ -37,7 +37,7 @@ target_2:
   #-------------------------------------------------------------
 
 test_3:
-  li  x28, 3
+  li  TESTNUM, 3
   li  x31, 0
   la  x3, target_3
 

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index a636a3605f768bf87d3a03a5f679eec40bc93ef1..fba7e78f83f9be1335f7c57d0af6ae1fda0311d0 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -34,7 +34,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -63,16 +63,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index e6190c9c99bad4160351136d3e91992dcaa3f348..f03b4437576fb2998bbf309045a752a75b074658 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -33,7 +33,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -62,16 +62,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index c16086e919747f29f524c8ee74ceb5642f5d811f..6896b8913f1412e04f490b561f7e83baeadcb752 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -40,7 +40,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -69,16 +69,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index ce4fe82bf8a49ec3a0d35215838822f896c1f442..c2400767239ec9f198559c4375308fe0635120b1 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -48,7 +48,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -77,16 +77,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index c48e134df4fed3b6b0c94e372857d705be632d3a..b139edf4a9ab0e738c8c2f492d9545e0aa01492c 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -44,7 +44,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -73,16 +73,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 3879d51faf7708b5d0a6241708502aa927317b97..56ece920734dc2683b3d6448bb2bd24f7e97186d 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -45,7 +45,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -74,16 +74,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index d66c42f879ac0d60b559037839a4bc23863c9e70..57b6bf901fba1498039cdd5e433a89b4a31da8af 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -45,7 +45,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -74,16 +74,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 715e6a2f2767b5d87b6db38e43e5c572ef605d58..90eb7922c708f10a8fb31ce47fb2471ef69cab77 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -48,7 +48,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -77,16 +77,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index c8ef5ad143c1df92fc95b6ea53119d969f8f1139..cd7762dc325ca3bcf1dbb2cdaa179c236a8fe384 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -38,7 +38,7 @@ vtcode1:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -67,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 1a88ca324cb74e7b9c3e18662ea7c146776bece9..ef50188b3f72bf95880b1e88845822977da6a19f 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -37,7 +37,7 @@ vtcode2:
 handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
   vxcptcause a3
@@ -67,16 +67,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL

diff --git a/isa/rv64ui/j.S b/isa/rv64ui/j.S
index 5b0ea3d321588c61df4db05b5eea0cf49b154b26..3c15dd3e96a1bc2bb6ef3395e4d374b12bb0ad83 100644 (file)
--- a/isa/rv64ui/j.S
+++ b/isa/rv64ui/j.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
   # Test basic
   #-------------------------------------------------------------
 
-  li  x28, 2;
+  li  TESTNUM, 2;
   j test_2;
   j fail;
 test_2:

diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S
index f51ce1b2c4aee3eb527698940ef10406498184b9..4881f9035d9241313bdd2944ab2ce8632bb667c9 100644 (file)
--- a/isa/rv64ui/jal.S
+++ b/isa/rv64ui/jal.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  ra, 0
 
 linkaddr_2:

diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index 9eef93b2de50d0ab52a08f478c0efb2465c25c41..cdf71e90d03ad9d5b9b1b923cc1c4320fbc79afc 100644 (file)
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN
   #-------------------------------------------------------------
 
 test_2:
-  li  x28, 2
+  li  TESTNUM, 2
   li  x31, 0
   la  x2, target_2
 
@@ -37,7 +37,7 @@ target_2:
   #-------------------------------------------------------------
 
 test_3:
-  li  x28, 3
+  li  TESTNUM, 3
   li  x31, 0
   la  x3, target_3
 

diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index 68b0ba15843873f2e8c3af8d74e645c51784a4b8..64386b2b36c348fc5a1b4e4f5a6e221249ed5894 100644 (file)
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
index ba798eff49abf4da2c7c559b57500e702391a3cf..3fcf25f2d069d268ffdec041d79d6187a7e08e14 100644 (file)
--- a/isa/rv64uv/amoadd_w.S
+++ b/isa/rv64uv/amoadd_w.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
index b2dc699f61a1bdba87ffc2b4f0ee9744ba60fc3c..f997ab096ba708f6aefc0453115ce6fe4f98ff18 100644 (file)
--- a/isa/rv64uv/amoand_d.S
+++ b/isa/rv64uv/amoand_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
index 726033d4b797553da8ff1a2b71c94ab77553236e..7cc39ea7a1289cd98c3af088128cd00282876d7f 100644 (file)
--- a/isa/rv64uv/amoand_w.S
+++ b/isa/rv64uv/amoand_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
index aafdf7548f68fabd4e8be6f7e11c6ff07d205084..c376b0e7c0145115fec296859b6259d58159ffed 100644 (file)
--- a/isa/rv64uv/amomax_d.S
+++ b/isa/rv64uv/amomax_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index 0308991ebfe557a63be97d082fcdbe3521b62c00..ec1c098ad9654507cc3195c7fa6d234ae46c95c7 100644 (file)
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
index 95d8fce64213d91ef89d5555f6750f18258694ee..696fb855acbe007a6581820be040797de0ad3686 100644 (file)
--- a/isa/rv64uv/amomaxu_d.S
+++ b/isa/rv64uv/amomaxu_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
index feac563418b2af9ab4c4ce34701237abece6acf1..3d7fd638e013b89e44ab5004fa9b075ab07d732f 100644 (file)
--- a/isa/rv64uv/amomaxu_w.S
+++ b/isa/rv64uv/amomaxu_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index 6fd9d2739dcbfdd719d53b87f63a4dd8499e79b5..5215c3bcb085a6d0cea6a6dbb550fc60b558f031 100644 (file)
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a5)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a5,a5,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
index 44260f2e1ffca1074c5e5a743a6cd033b431eeac..0b822fa4f3894670ace08587cec2d3e35540fe6a 100644 (file)
--- a/isa/rv64uv/amomin_w.S
+++ b/isa/rv64uv/amomin_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
index 3f5f7abf74a8a232c5a3e85f44fd121c3822f90b..4c0b31f5a9e837d4e3e2b49cdee8dbab4f015ad5 100644 (file)
--- a/isa/rv64uv/amominu_d.S
+++ b/isa/rv64uv/amominu_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 56f3a7dc68b69e89ee87e397e98bbb0845ea512d..1cc8b2459b9fd74d84d32a5403474d632edd6555 100644 (file)
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index 76d553c7bbdbe8ea111e3f1c86cd764d12c06208..833f0561f5ca0b069451acf5b721c8658d84046a 100644 (file)
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 9d0bd2fc6a04316e4d37f30e66ce7284dc672b22..c948c329fc396b593bab3f035af32f703e134afd 100644 (file)
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
index df9855637035bfacd3eba5856a43559851907060..0e3db8f6a6ec7a84db8dc60526d59ba96a631218 100644 (file)
--- a/isa/rv64uv/amoswap_d.S
+++ b/isa/rv64uv/amoswap_d.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
index c06856923db4f1a320c9b74fefae9ab920dfbab4..6a5b1fb7f526955f4e5e02a392e9ee5067cdd00d 100644 (file)
--- a/isa/rv64uv/amoswap_w.S
+++ b/isa/rv64uv/amoswap_w.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/amoxor_d.S b/isa/rv64uv/amoxor_d.S
index f67bccfb4923c97074cec1062c38e26a297fef9c..7f84fd55f7c42cd598317933d42fc1c3504dfa7a 100644 (file)
--- a/isa/rv64uv/amoxor_d.S
+++ b/isa/rv64uv/amoxor_d.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   li t0,0xaaaaaaaaaaaaaaaa
 loop:
   ld a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,8
   addi a1,a1,1

diff --git a/isa/rv64uv/amoxor_w.S b/isa/rv64uv/amoxor_w.S
index fac070f124d3235bccea92fb1f9b545e171769c0..602634ddd265c29f380f70f4edb61a25bfd2513c 100644 (file)
--- a/isa/rv64uv/amoxor_w.S
+++ b/isa/rv64uv/amoxor_w.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1

diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
index 227a154ce9fa110a35c90cb7336304e93e4891b5..cb8e98cdf3a407d6240a1292d6a7e69c3cd63c39 100644 (file)
--- a/isa/rv64uv/fcvt.S
+++ b/isa/rv64uv/fcvt.S
@@ -25,19 +25,19 @@ RVTEST_CODE_BEGIN
   la a5,result
   ld a1,0(a4)
   ld a2,0(a5)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a4)
   ld a2,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a4)
   ld a2,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a4)
   ld a2,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 

diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index d41e76122a80d2e7c7bf09b20c33024ce9e5f367..37e05e06f83761405f3d436f4889e829750284de 100644 (file)
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   ld a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,8

diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index 7e940f6db82fc33e6f19b0175bb5ee5e46dc9d60..02844894ae33698ba7a8582b98b1c512ab5d064a 100644 (file)
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4

diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
index e875c61924ea785279da4dbf4677d85e1bde630e..c4489aedaaf328a52d7ea0661c1eda70f85d05f5 100644 (file)
--- a/isa/rv64uv/fma.S
+++ b/isa/rv64uv/fma.S
@@ -40,13 +40,13 @@ wait:
 
   la s3,result
   ld s4,0(s3)
-  li x28,2
+  li TESTNUM,2
   bne s2,s4,fail
 
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,s4,fail
   addi a5,a5,8
   addi a2,a2,1

diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index 47a6a3936d5e20ed291d89e91c81177ae16ed5bf..6c54b5e601582ce583478b7c4bff5eac789d7c8d 100644 (file)
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -29,7 +29,7 @@ loop:
   slli a4,a4,63
   srai a4,a4,63
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1

diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
index f3e09b65f18b44f58136730b708ad7ec0393ba7f..4f55cdcec4cf2501d79768f397b6bb34b033d57e 100644 (file)
--- a/isa/rv64uv/fmovz.S
+++ b/isa/rv64uv/fmovz.S
@@ -30,7 +30,7 @@ loop:
   srai a4,a4,63
   xori a4,a4,-1
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1

diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
index f22067988f74bcd35229e1e594630874774a4c27..c871e09ceba89609a18c75ab310420ad59adf552 100644 (file)
--- a/isa/rv64uv/fsd.S
+++ b/isa/rv64uv/fsd.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   ld a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   ld a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,8

diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index 71c1d2f057a7ae4bf8cec86dde715e6070c6685a..7c78df583638449e14609f196ab3aba7d4bba796 100644 (file)
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a2,0
 loop:
   lw a0,0(a6)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   lw a1,0(a5)
   bne a0,a1,fail
   addi a6,a6,4

diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index 1b3a2dd71a70b1dda7e3dd1164ab586d93a38b2a..554374d262e51b20aed58897d727f6f8db4d2ba4 100644 (file)
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -48,14 +48,14 @@ RVTEST_CODE_BEGIN
   fence
 
   li s2,40
-  li x28,2
+  li TESTNUM,2
   bne s1,s2,fail
 
   li a1,0
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,a1,fail
   addi a5,a5,8
   addi a1,a1,20

diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
index 46ca639b09ab0a21d4cd3f800f727b333ca7b341..471199a3a3a74d1d0ddb43d816f5f27eacb0adc2 100644 (file)
--- a/isa/rv64uv/lb.S
+++ b/isa/rv64uv/lb.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   sra a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 47c226151c0c1b5b12431c69455af1d0a6e37ee1..2aa5ee8d64d2c6fcf26f2810b08351c9b81cae54 100644 (file)
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index 354ee38531f87e329acb5b3da19e8e83ba5cb0d6..07941921637e23f2a2284ec723591a124fc30ba3 100644 (file)
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
 loop:
   ld a0,0(a6)
   ld a1,0(a5)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
index e4ff17663821bf7cf0ec76fe7e00f52f08e559b5..a24146c313d5de5756bbe7dd19b9034011b966e4 100644 (file)
--- a/isa/rv64uv/lh.S
+++ b/isa/rv64uv/lh.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   sra a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
index dadf99be349c01872d3abc44413cd79bf002b2c7..e20d56d72dda077ccfed6655b781b9ce32356275 100644 (file)
--- a/isa/rv64uv/lhu.S
+++ b/isa/rv64uv/lhu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   srl a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 182dc8952e522d8feb140b9fc55c26f6ed2a38d7..b40ec47ab78d02adf148105984abb00d93d722a5 100644 (file)
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   sra a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index d6df8396ae9f647b2f09c3e9b8dfa40e0b4633b9..0b3591a43ff2778941818a895e972b730ec7031f 100644 (file)
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -29,7 +29,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   srl a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
index 374b271c378406971f6522430ff31d7f384e5cc1..790edce68efc0fa90306b95797c6e88292f491eb 100644 (file)
--- a/isa/rv64uv/movz.S
+++ b/isa/rv64uv/movz.S
@@ -30,7 +30,7 @@ loop:
   srai a4,a4,63
   xori a4,a4,-1
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1

diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index 5cbe76aeb7feaca09ac7dbd257c790e8f91a5ee1..b9954edd76a66912da4cf5d465f2645601feb41d 100644 (file)
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,56
   srl a3,a3,56
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index 053c401fe24b8b7bf96e21c7c474dbcb98acf693..5ec80513aa1de4592d1b9360e31fe4003b488343 100644 (file)
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -27,7 +27,7 @@ RVTEST_CODE_BEGIN
 loop:
   ld a0,0(a6)
   ld a1,0(a5)
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a1,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index 25bb258dbe4b893d104a9232b2aa8e7fcac8303e..01770106e5eed1509f0912d725e44434f1f96a5c 100644 (file)
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,48
   srl a3,a3,48
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 8f1599b72893f5d3662e7ba6ddf655ff54c07984..61967202821ad57715f0e1857e14c4e51f30449f 100644 (file)
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -39,7 +39,7 @@ loop:
   ld a1,0(a5)
   sll a3,a1,32
   srl a3,a3,32
-  addi x28,a2,2
+  addi TESTNUM,a2,2
   bne a0,a3,fail
   addi a6,a6,8
   addi a5,a5,8

diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 04391151af7c6a356c48207b3f59fa0225aa02a0..a672776dd792da1e42298018418bfb928bc4bef0 100644 (file)
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -24,7 +24,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1

diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 68e085ea14f79893308b6165305f0ba76d144ad9..cb97dee058f035542ac659cdbb2b06afb50bff07 100644 (file)
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a3)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a3,a3,8
   addi a1,a1,1

diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
index d469e59b5e86f65176390a1aa56f81aca645582c..773188dc61a03877822fe6d876237c8b99b606c8 100644 (file)
--- a/isa/rv64uv/vmsv.S
+++ b/isa/rv64uv/vmsv.S
@@ -26,7 +26,7 @@ RVTEST_CODE_BEGIN
   li a1,0
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1

diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index be1adb3c07b2cfba4880bb5d37cf4040e00320f2..b546f0526b1f2702d113db3eb72f02ad7f4f6b1a 100644 (file)
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -25,7 +25,7 @@ RVTEST_CODE_BEGIN
   li a1,1
 loop:
   ld a0,0(a4)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a1,fail
   addi a4,a4,8
   addi a1,a1,1

diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 5f9f3a424c1a448e5d44b25a9b605f6fb8c58ffb..4c3fefe2dd1787985a67e6b013ed0af4e2f46c56 100644 (file)
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -27,19 +27,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,8
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
   li a2, 6        
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
   li a2, 4        
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   li a2, 2
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   la a3,src1
@@ -54,19 +54,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,1
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,2
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,0
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,0
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   la a3,src2
@@ -79,19 +79,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,4
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,3
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,2
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,1
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   j pass

diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
index 8875b9565f7b1071fcbc63d945b0e3a7461dfa2d..e1acea7e03d58d5dde63d0420bbb76f608668abf 100644 (file)
--- a/isa/rv64uv/vvadd_d.S
+++ b/isa/rv64uv/vvadd_d.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   la a3,src1
@@ -49,19 +49,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,1
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,2
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,3
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,4
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   la a3,src2
@@ -74,19 +74,19 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,4
-  li x28,6
+  li TESTNUM,6
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,3
-  li x28,7
+  li TESTNUM,7
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,2
-  li x28,8
+  li TESTNUM,8
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,1
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
 
   j pass

diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 62161efef8a7a5960df9ebcbed168afefbb9a5a4..a9961afb7c0459f4424b54ffda10823260fc3409 100644 (file)
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
   la a6,result
   ld a1,0(a5)
   ld a2,0(a6)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 

diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
index 916002ff3ba9db79d30842d7f00010a71b67e96c..e40fd013480f97d51706d12fe0825b9f9dbbdf65 100644 (file)
--- a/isa/rv64uv/vvadd_fw.S
+++ b/isa/rv64uv/vvadd_fw.S
@@ -27,16 +27,16 @@ RVTEST_CODE_BEGIN
   la a6,result
   lw a1,0(a5)
   lw a2,0(a6)
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   lw a1,4(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   lw a1,8(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   lw a1,12(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 

diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index f81c42e07a08f895cfa73ddd56dee5b74f13f2bf..9fbcf491af7f715fde3ebc387f438dcc6743a0ac 100644 (file)
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -26,16 +26,16 @@ RVTEST_CODE_BEGIN
   fence
   lw a1,0(a5)
   li a2,10
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   lw a1,4(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   lw a1,8(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   lw a1,12(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 

diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
index a6a9d4a4fdab743f56fae24c53ab430412fc1f64..ae995c915798a3ea724e77a4c0b40058ff36bc66 100644 (file)
--- a/isa/rv64uv/vvmul_d.S
+++ b/isa/rv64uv/vvmul_d.S
@@ -26,19 +26,19 @@ RVTEST_CODE_BEGIN
   fence
   ld a1,0(a5)
   li a2,4
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
   li a2,6
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
   li a2,6
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
   li a2,4
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass
 

diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
index 008423a28cd29d9bf49f71ea5da8032d90d0695c..958f6688f6543afb5aeeaeb33fd41a7a6f2fcfb1 100644 (file)
--- a/isa/rv64uv/wakeup.S
+++ b/isa/rv64uv/wakeup.S
@@ -29,35 +29,35 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   # check default hw vector length, which is 32
   li a3, 32
   vsetvl a3, a3
   li a0, 32
-  li x28, 6
+  li TESTNUM, 6
   bne a3, a0, fail
 
   li a3, 33
   vsetvl a3, a3
   li a0, 32
-  li x28, 7
+  li TESTNUM, 7
   bne a3, a0, fail
 
   li a3, 31
   vsetvl a3, a3
   li a0, 31
-  li x28, 8
+  li TESTNUM, 8
   bne a3, a0, fail
 
   # now do some vector stuff without vsetcfg
@@ -77,16 +77,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,5
-  li x28,9
+  li TESTNUM,9
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,10
+  li TESTNUM,10
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,11
+  li TESTNUM,11
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,12
+  li TESTNUM,12
   bne a1,a2,fail
 
   # initialize dest memory
@@ -112,16 +112,16 @@ RVTEST_CODE_BEGIN
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe
-  li x28,13
+  li TESTNUM,13
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,14
+  li TESTNUM,14
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,15
+  li TESTNUM,15
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,16
+  li TESTNUM,16
   bne a1,a2,fail
 
   j pass