Test mstatus.TW, mstatus.TVM, and mstatus.TSR features

diff --git a/env b/env
index 00d8922398c202c13d6eb5da07e92be6364309a1..497efbd0fa104b70f058ea550ed0c7f8a554662b 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 00d8922398c202c13d6eb5da07e92be6364309a1
+Subproject commit 497efbd0fa104b70f058ea550ed0c7f8a554662b

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index 30c22b264fcadf55d66d5673e7d283fae18d9bda..8701a76910d5f0503ad5e8013211a42b7500158a 100644 (file)
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -14,10 +14,75 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   li TESTNUM, 2
 RVTEST_CODE_BEGIN
 
   li TESTNUM, 2

+bad2:

   .word 0
   j fail
 
   .word 0
   j fail
 

-  j pass
+  # Skip the rest of the test if S-mode is not present.
+  li t0, MSTATUS_MPIE
+  csrc mstatus, t0
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  li t1, (MSTATUS_MPP & ~(MSTATUS_MPP << 1)) * PRV_S
+  csrs mstatus, t1
+  csrr t2, mstatus
+  and t2, t2, t0
+  bne t1, t2, pass
+
+  # Set a software interrupt pending so WFI won't stall.
+  csrwi mideleg, MIP_SSIP
+  csrwi mip, MIP_SSIP
+  csrwi mie, MIP_SSIP
+  la t0, 1f
+  csrw mepc, t0
+  mret
+
+1:
+  # Make sure WFI doesn't trap when TW=0.
+  wfi
+bad3:
+  .word 0
+  j fail
+
+bad4:
+  # Make sure WFI does trap when TW=1.
+  wfi
+  j fail
+
+  # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
+  sfence.vma
+  csrr t0, sptbr
+bad5:
+  .word 0
+  j fail
+
+bad6:
+  # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
+  sfence.vma
+  j fail
+bad7:
+  csrr t0, sptbr
+  j fail
+
+  # Make sure SRET doesn't trap when TSR=0.
+  la t0, bad8
+  csrw sepc, t0
+  li t0, SSTATUS_SPP
+  csrs sstatus, t0
+  li t0, SSTATUS_SPIE
+  csrc sstatus, t0
+  sret
+bad8:
+  .word 0
+  j fail
+
+  # Make sure SRET does trap when TSR=1.
+  la t0, 1f
+  csrw sepc, t0
+bad9:
+  sret
+1:
+  j fail

 
   TEST_PASSFAIL
 
 
   TEST_PASSFAIL
 


@@ -26,10 +91,49 @@ mtvec_handler:
   csrr t0, mcause
   bne t0, t1, fail
   csrr t0, mepc
   csrr t0, mcause
   bne t0, t1, fail
   csrr t0, mepc

+  la t1, bad2
+  beq t0, t1, 2f
+  la t1, bad3
+  beq t0, t1, 3f
+  la t1, bad4
+  beq t0, t1, 4f
+  la t1, bad5
+  beq t0, t1, 5f
+  la t1, bad6
+  beq t0, t1, 6f
+  la t1, bad7
+  beq t0, t1, 7f
+  la t1, bad8
+  beq t0, t1, 8f
+  la t1, bad9
+  beq t0, t1, 9f
+  j fail
+2:
+4:
+6:
+7:

   addi t0, t0, 8
   csrw mepc, t0
   mret
 
   addi t0, t0, 8
   csrw mepc, t0
   mret
 

+3:
+  li t1, MSTATUS_TW
+  csrs mstatus, t1
+  j 2b
+
+5:
+  li t1, MSTATUS_TVM
+  csrs mstatus, t1
+  j 2b
+
+8:
+  li t1, MSTATUS_TSR
+  csrs mstatus, t1
+  j 2b
+
+9:
+  j pass
+

 RVTEST_CODE_END
 
   .data
 RVTEST_CODE_END
 
   .data